Method for forming cell capacitor for high-integrated DRAMs

ABSTRACT

A method for forming a cell capacitor used for a high-integrated DRAM is disclosed which guarantees interfacial properties of aluminum oxide and excellent leakage current preventive properties by depositing an aluminum oxide layer and a mixed layer of TiON and TiO 2  as dielectric layers on a semiconductor substrate having a predetermined lower substructure by an atomic layer deposition (ALD) method and thus forming a double layer structure, and simultaneously providing a high capacitance by using a high dielectric property of a mixed layer of TiON and TiO 2 .

BACKGROUND

[0001] 1. Technical Field

[0002] A method for forming a cell capacitor for a high-integrated DRAM which provides good interfacial properties of aluminum oxide and excellent leakage current preventive properties by depositing an aluminum oxide layer and a mixed layer of TiON and TiO₂ as dielectric layers on a semiconductor substrate having a predetermined lower substructure by an atomic layer deposition (ALD) method and thus forming a double layer structure, and simultaneously providing a high capacitance by using a high dielectric property of a mixed layer of TiON and TiO₂.

[0003] 2. Description of the Related Art

[0004] Recently, with the development of semiconductor integrated circuit processing techniques, the minimum line width of a device manufactured on a semiconductor substrate is getting miniaturized and unit area integration degree is getting increased. Meanwhile, as the integration degree of a memory cell increases, a space occupied by a cell capacitor for charge storage becomes smaller. Thus, it is necessary to develop a cell capacitor having an increased unit area capacitance.

[0005] Generally, a capacitor is a part for storing charge and supplying charge needed for the operation of a semiconductor substrate. As the semiconductor is becoming highly integrated, the size of a unit cell is becoming smaller and the capacitance required for the operation of the device is being increased.

[0006] The structure of a charge storage electrode of the capacitor is divided broadly into a stacked structure for acquiring a large capacitor area by stacking multi-layers on a narrow planar area and a trench structure for storing charge by forming a trench of a predetermined depth on a semiconductor substrate and then forming a capacitor on that portion.

[0007] Particularly, efforts for increasing the charging capacitance of the capacitor are made by constructing the stacked structure as a deformed capacitor structure such as HSG (hemispherical shaped grains), bellows, etc. which are formed by deforming a fin type, a cylinder type and a cavity type.

[0008] In a conventional art, with the high integration of semiconductor devices, capacitors also are required to be miniaturized. However, there is a limitation on storing charge, so there occurs a difficulty in highly integrating the capacitor as compared with the size of a cell.

[0009] Therefore, to solve the above problem, a material with a high dielectric constant such as TiON is used for increasing the charge of the capacitor, however, which leads to a high leakage current in performing the subsequent process.

[0010] In addition, in the case that aluminum oxide is used for guaranteeing a low leakage current, interfacial properties and leakage current properties are excellent, but capacitance is low.

SUMMARY OF THE DISCLOSURE

[0011] A method for forming a cell capacitor for a high-integrated DRAM is disclosed which provides good interfacial properties of aluminum oxide and excellent leakage current preventive properties by depositing an aluminum oxide layer and a mixed layer of TiON and TiO₂ as dielectric layers on a semiconductor substrate having a predetermined lower substructure by an atomic layer deposition (ALD) method and thus forming a double layer structure, and simultaneously provides a high capacitance by using a high dielectric property of a mixed layer of TiON and TiO₂.

[0012] A method for forming a cell capacitor for a high-integrated DRAM in accordance with the disclosure comprises: depositing a first dielectric layer on a semiconductor substrate having a predetermined lower structure; performing an annealing process under nitrogen atmosphere again after performing a plasma annealing process on the resultant material; performing a low temperature annealing and a furnace vacuum annealing processes after depositing a second dielectric layer on the resultant material; and depositing sequentially a titanium nitride layer and a poly silicon layer on the resultant material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above, features and advantages of the disclosed methodology will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0014]FIGS. 1a through 1 d are cross-sectional views sequentially illustrating a method for forming a cell capacitor for a high-integrated DRAM in accordance with the present invention.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0015] Preferred embodiments will now be described with reference to the accompanying drawings.

[0016]FIGS. 1a through 1 d are cross-sectional views sequentially illustrating a method for forming a cell capacitor used for a high-integrated DRAM in accordance with the disclosed methods.

[0017] As illustrated in FIG. 1a, aluminum oxide is deposited as a first dielectric layer 110 on a semiconductor substrate 100 having a predetermined lower substructure by an ALD (atomic layer deposition) method.

[0018] At this time, the first dielectric layer 110 is deposited on the semiconductor substrate 100 heated at a temperature ranging from about 200 to about 450° C. in a chamber having a pressure ranging from about 0.1 to about 1 Torr by using vapor.

[0019] Then, as illustrated in FIG. 1b, carbon and impurities in the aluminum oxide are removed by performing a N₂O plasma annealing process 120 on the resultant material at a temperature ranging from about 300 to about 400° C., and then the aluminum oxide layer (the first dielectric layer 110) is crystallized by performing an annealing process under nitrogen atmosphere a time period ranging from about 10 to about 30 minutes at a temperature ranging from about 600 to about 650° C.

[0020] Continuously, as illustrated in FIG. 1c, a mixture of TiON(A) and TiO₂(B) is deposited on the resultant material as a second dielectric layer 130 by using the ALD (atomic layer deposition) method, and then a furnace vacuum anneal process is performed.

[0021] At this time, as the second dielectric layer 130, a TaON layer(A) is deposited on the semiconductor substrate heated at a temperature ranging from about 250 to about 350° C. to a thickness of below about 10 Å by the ALD (atomic layer deposition) method. To prevent residue of each material from being remained, inert gas such as N₂, Ar, He, etc. is injected between the injection of Ta(OC₂H₅)₅ source gas and the injection of reactive material NH₃ gas.

[0022] In addition, in the ALD (Atomic Layer Deposition) method, when the injection of Ta(OC₂H₅)₅ source gas, the injection of inert gas such as N₂, Ar, He, etc. and the injection of NH₃ gas are achieved in one cycle, the thickness of the TaON layer(A) deposited per cycle ranges from about 0.1 to about 1 Å, thus enabling the deposition of a layer with a thickness ranging from about 0.1 to about 10 Å.

[0023] Then, a TiO₂ layer(B) is deposited to a thickness of below 5 Å by the ALD (Atomic Layer Deposition). To prevent residue of each material from being remained, inert gas such as N₂, Ar, He, etc. is injected between the injection of Ta(OC₂H₅)₅ source gas and the injection of reactive material NH₃ gas.

[0024] At this time, in the ALD (atomic layer deposition) method, when the injection of TiCl₄ source gas, the injection of inert gas such as N₂, Ar, He, etc. and the injection of at least one of H₂O, O₂ and N₂O gases are achieved in one cycle, the thickness of the TaON layer(A) deposited per cycle ranges from about 0.1 to about 1 Å, thus enabling the deposition of a layer with a thickness ranging from about 0.1 to about 5 Å.

[0025] At this time, the injection time of each gas ranges from about 0.1 to about 10 sec.

[0026] In addition, by controlling the cycle so that the deposition ratio of the TaON layer(A) and the TiO₂ layer(B) is (90˜92):(8˜10), the TaON layer(A) and the TiO₂ layer are alternately deposited to a thickness ranging from about 100 to about 200 Å.

[0027] Moreover, the TaON layer(A) and the TiO₂ layer alternately deposited are changed into a single mixed layer by low temperature annealing. In the furnace vacuum annealing process, impurities in the second dielectric layer 130 are removed and crystallized by performing the annealing for a time period ranging from about 5 to about 60 minutes at a temperature ranging from about 600 to about 850° C.

[0028] Continuously, as illustrated in FIG. 1d, a titanium nitride layer 140 is deposited on the resultant material as an upper electrode to a thickness ranging from about 200 to about 500 Å, and then a polysilicon layer 150 is sequentially deposited to a thickness ranging from about 900 to about 1100 Å.

[0029] Accordingly, in the method for forming a cell capacitor used for a high-integrated DRAM, interfacial properties of aluminum oxide and excellent leakage current preventive properties are guaranteed by depositing an aluminum oxide layer and a mixed layer of TiON and TiO₂ as dielectric layers on a semiconductor substrate having a predetermined substructure by an atomic layer deposition (ALD) method and thus forming a double layer structure, and simultaneously a high capacitance is guaranteed by using a high dielectric property of a mixed layer of TiON and TiO₂. 

What is claimed is:
 1. A method for forming a cell capacitor for a high-integrated DRAM comprising: depositing a first dielectric layer on a semiconductor substrate having a predetermined lower structure; performing an annealing process under nitrogen atmosphere after performing a plasma annealing process; performing a low temperature annealing and a furnace vacuum annealing after depositing a second dielectric layer on the first dielectric layer; and sequentially depositing a titanium nitride layer and a poly silicon layer on the second dielectric layer.
 2. The method of claim 1, wherein the first dielectric layer comprises Al₂O₃.
 3. The method of claim 1, wherein the first dielectric layer is deposited on the semiconductor substrate in a chamber containing vapor and that is heated to a temperature ranging from about 200 to about 450° C. a pressure ranging from about 0.1 to about 1 Torr.
 4. The method of claim 1, wherein, in the plasma annealing, N₂O plasma is used at a temperature ranging from about 300 to about 400° C.
 5. The method of claim 1, wherein the annealing process is performed under a nitrogen atmosphere for a time period ranging from about 10 to about 30 minutes and at a temperature ranging from about 600 to about 650° C.
 6. The method of claim 1, wherein the second dielectric layer is formed by depositing alternately a TaON layer and the TiO₂ layer each with a thickness ranging from about 100 to about 200 Å by a ALD method, so that a deposition ratio of the TaON layer and the TiO₂ layer is within the ranges (90˜92):(8˜10).
 7. The method of claim 1, wherein the TiON layer is formed with a thickness ranging from about 0.1 to about 10 Å by injecting alternately Ta(OC₂H₅)₅ gas and NH₃ gas.
 8. The method of claim 1, wherein, in the forming of the TiON layer, inert gas is injected between the injection of the Ta(OC₂H₅)₅ gas and the injection of the NH₃ gas.
 9. The method of claim 1, wherein the TiO₂ layer is formed with a thickness ranging from about 0.1 to about 5 Å by injecting alternately TiCl₄ source gas and H₂O gas.
 10. The method of claim 1, wherein, in the of forming the TiO₂ layer, inert gas is injected between the injection of the TiCl₄ gas and the injection of the H₂O gas.
 11. The method of claim 1, wherein the low temperature annealing is performed at a temperature ranging from about 400 to about 550° C., and the furnace vacuum annealing is performed at a temperature ranging from about 600 to about 850° C. and for a time period ranging from about 5 to about 60 minutes.
 12. The method of claim 1, wherein the titanium nitride layer is deposited with a thickness ranging from about 200 to about 500 Å, and the polysilicon layer is deposited with a thickness ranging from about 900 to about 1100 Å.
 13. A semiconductor integrated circuit comprising a cell capacitor formed in accordance with the method of claim
 1. 14. A DRAM comprising a cell capacitor formed in accordance with the method of claim
 1. 